1. Field of the Invention
This invention relates to analog-to-digital (A/D) converters. More particularly, this invention relates to such converters which are capable of fast conversion to at least 12-bit resolution, and which are formed monolithically as an integrated-circuit (IC) chip.
2. Description of the Prior Art
A wide variety of monolithic A/D converters have been proposed heretofore, but none has met the need for high-speed conversion with at least 12 bits resolution. For example, it has been known that high speed conversion can be effected through the use of so-called flash converters, wherein all of the output bits are determined essentially simultaneously. However, to achieve the desired 12-bit resolution with a flash converter would require 2.sup.12 -1 (or 4095) comparators, which is not practical in a monolithic realization.
It also is known that the total number of comparators in a flash converter can be reduced by operating such a converter through a sequence of "sub-ranging" cycles wherein the converter in the first cycle determines a first set of higher-order bits, and in subsequent cycles determines respective sets of lower-order bits so as to produce a final digital output signal as a composite of the digital outputs developed during the successive cycles. At the end of each cycle the flash converter digital output is supplied to a D/A converter which produces an analog output to be subtracted from the analog input signal to produce a "residue" error signal for the next cycle conversion. The number of bits developed by the flash converter in each such sub-ranging cycle is only a fraction of the number of bits in the final composite digital output, and thus much fewer comparators are needed.
Although the principle of such sub-ranging A/D converters is well known, no fully commercially satisfactory 12-bit (or higher resolution) converter of that type has been provided in monolithic form. Examination of the technical requirements for such a converter will make it evident that a number of serious problems must be overcome to produce a converter having the requisite accuracy, resolution and speed. It is a general object of the present invention to solve those problems.
One particularly difficult problem is the need to overcome the performance inadequacies of flash converter designs known heretofore. For example, such converters commonly have suffered from poor dynamic response chracteristics, with the response being dependent upon input signal level. Also, the comparators in prior art designs typically did not all respond identically, e.g. due to differences in base current loading among the comparators.
Another serious obstacle in providing a monolithic sub-ranging A/D converter is the relatively large gain change required to achieve the different flash resolutions for the sequence of sub-ranging cycles. For example, for a 12-bit converter operated at 3-bits per sub-ranging cycle, the total net gain change between the first and fourth cycles must be 1:512. This is very difficult to achieve in conventional ways.
A still further problem is encountered in providing an acceptable arrangement for amplifying the "residue" error, i.e. the difference between the analog input signal and the analog output of the D/A converter controlled by the flash converter. Conventionally, the residue amplifier would be an op amp referenced to zero (ground), and connected in a negative feedback circuit. However, it is very difficult to achieve satisfactory operation with such a circuit in monolithic format.